Programmable logic

In designing programmable logic for FPGAs, we use a method that is strongly related to software development. Reusability, repeatability and consistency are important aspects. We begin to test very early on in the process and continue to test throughout. This can prevent time loss later on, during product development.

Nightly build, RDL and IP integration

Our long expertise and the reuse of IPs allow us to realize reliable programmable logic in a short time span. We use RDL to automatically generate System-on-Chip interconnect/bus structures to connect IP building blocks with each other. This means that the programmable logic and (embedded) software are based on the same definition; this ensures consistency and reliability. A nightly build is run every day, performing automatic verification and validation of the logical components and embedded software that have been produced. This ensures that any errors are detected and solved early on in the development process. Our automated design and testing process allows us to offer consistency and repeatability in every design iteration.

High-level testing

We use hardware/software co-simulation (on the basis of Cocotb) to develop co-routines that are invoked in simulation to test the programmable logic automatically and in a scripted way. This makes it possible to rapidly devise tests at a high level, and to use generic software functions (such as Python) to carry out unit tests. This means testing begins at a very early stage of the design. This results in higher quality and greater reliability for your final product.

Independent of FPGA technology

Our approach uses RDL, nightly build and automated scripting, and this means we can generate the created programmable logic for any FPGA, so that our solutions are truly supplier-independent. To give one example of the possibilities: we have made a full RISC-V processor of our own that we can use for any FPGA supplier.